By Truman T.E.
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Extra resources for A methodology for the design and implementation of communication protocols for embedded wireless systems
Functional issues, on the other hand, are often dealing with corner cases that are difficult to exercise using simulation tools and are typically addressed using formal verification. In this section, we provide a few selected examples from this InfoPad system that illustrate how one moves from a high-level informal specification to specific service requirements, and show how the service requirements can be broken into performance estimation issues and verification issues. First, we identify the primary services that our protocols are to provide: 36 1) Data link: provides an unreliable, point-to-point “bit pipe” between the InfoPad and a basestation 2) Media access: provides a means by which multiple InfoPad devices can physically share the same airspace, minimally interfering with each other Data Stream Uplink Downlink Video -- 400 Kbits/s Audio/Speech 64 Kbits/s 64 Kbits/s Pen 8 Kbits/s -- Graphics -- 128 Kbits/s Control < 1Kbit/s < 1Kbit/s Total ~ 75 Kbits/s ~ 600 Kbits/s Table 2— 1.
9 At the heart of the issue is that hardware and software naturally have two very different types of concurrency – interleaved and true parallel – and so design styles, representations, and simulation semantics are extremely domain-specific. We will explore these issues further in Chapter 3. Summarizing, we are presented with conflicting objectives in our specification languages, in our ways of checking “correctness”, and it becomes difficult to relate these various conceptual models to the domain of our implementation.
Simulation is then used to drive the bulk of the algorithmic exploration, and the results of these simulations are used to elaborate and fine-tune the original design. Typically, it is only after a prototype of the system has been built and checked via 15 black-box conformance testing [Hol92] that the system is checked against the standard. LLC Formal Verification (Promela) Hardware Design (SMV/ Verilog) Functional Reqt’s Formal Spec (Message Sequence Charts) Formal Model (SDL) Software Design (C/C++/ASM) Perf.