Authentication and access control in the JPEG 2000 by Grosbois, Gerbelot, Ebrahimi

By Grosbois, Gerbelot, Ebrahimi

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Example 4-9 contains two initial blocks and an always block. The first initial block has only one statement in it: a delay of 50 time units and a $finish statement. The first initial statement is necessary to make the simulation terminate; without this statement, the always block would keep the simulation running forever. Example 4-9 Combining begin-end and fork-join Blocks module befjia; initial # 50 $finish; initial begin #1 $display(" b 1") ; #1 fork b 1 f 1") ; #1 $display( " $display(" b 1 f 2") ; #5 $display( " b 1 f 3") ; #2 begin $display(" b 1 f 4 b 1"); #1 $display(" b 1 f 4 b 2") ; $display(" b 1 f 4 b 3") ; end join $display(" b 2"); end always fork # 3 $display(" f 1") ; begin f 2 b 1"); #1 $display(" f 2 b 2"); #2 $display(" f 2 b 3") ; #3 $display(" end begin 42 Verilog Quickstart #10 $display(" #9 $display(" #8 $display(" f 3 b 1"); f 3 b 2") ; f 3 b 3") ; end # 5 fork #1 $display(" #2 $display(" #3 $display(" join # 1 $display(" f 4 f 1") ; f 4 f 2") ; f 4 f 3") ; f 5") ; join endmodule Notice that the always block will repeat when the fork-join block finishes running.

Figure 3-8 Adder2 Schematic Connect two of the adder2s together to form a 4-bit adder as shown in Figure 3-9. 30 Verilog Quickstart Figure 3-9 Adder4 Schematic Connect two of the adder4s together to form a 8-bit adder as shown in Figure 3-10. v shown in Example 3-8. You should get the results as shown in Example 3-8 Results. == 219) begin $display("sum is wrong" ) ; $finish; end $finish ; end endmodule 31 32 Verilog Quickstart Note that the results of this simulation, shown in Example 3-8 Results, did not give us any meaningful results other than the fact that it finished at time 600.

Thus far in the book you have seen three modules: the phone module, the mux module, and the hello module. SEMICOLONS Each Verilog statement ends with a semicolon. The only lines that do not need semicolons are those lines with keywords that end a statement themselves, such as endmodule. Figure 2-2 The Mux Example Let’s look at the mux example we used before and explain each line. Example 2-9 Gate-Level Mux Verilog Code 1 2 3 4 5 6 7 8 9 10 • • module mux(OUT, A, B, SEL); output OUT; input A,B,SEL; not I5 (sel_n, SEL); and I6 (sel_a, A, SEL); and I7 (sel_b, sel_n, B); or I4 (OUT, sel_a, sel_b); endmodule Line 1: module mux(OUT, A, B, SEL); This line declares the module name and its list of ports.

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